Wednesday , January 27 2021

Intel reveals a new architecture for 2019: Sunny Cove

Ok, it's not that sunny, but it's a good picture of a bay.

Ok, it's not that sunny, but it's a good picture of a bay.

In 2019, Intel Core and Xeon chips release, built around a new architecture: the chips will add a lot of new instructions to speed up certain popular workloads such as cryptography and compression. The company demonstrates an improvement of 75 percent in compression performance over previous generations.

Since 2015, Intel's mainstream processors under the Core and Xeon brands have been based on the Skylake architecture. Intel's original intention was to release Skylake on its 14nm manufacturing process and then follow it up with Cannon Lake on its 10nm process. Cannon Lake will add a handful of new features (it includes, for example, more AVX instructions), but otherwise it's pretty much the same as Skylake.

Delays in getting its 10nm production process efficiently forced Intel to hold 14nm longer than expected. Consequently, the company followed Skylake (with up to four cores in consumer systems) with Kaby Lake (with higher clock speeds and much greater hardware acceleration of modern video codecs), Coffee Lake (as many as eight cores) and Whiskey Lake (Whiskey Lake enhanced integrated chipset). The core Skylake architecture was unchanged across these variations, which means that while their clock speeds are different, the number of instructions per. Cycle (IPC) essentially identical.

Looking at the sunny side of 10nm

Intel says that Sunny Cove, on the other hand, is an improved micro architecture that has to be built on the company's 10nm process. While it is still derived from Skylake, it has been improved to perform more instructions in parallel and with lower latency, and some buffers and caches have also been enlarged. Level 1 data cache is 50 percent greater than in Skylake, like the decoded micro ops and level 2 cache (with the exact size depending on market positioning). Where Skylake has two reservation stations that send instructions across eight ports with no more than four instructions sent per. Cycle, Sunny Cove has four reservation stations, ten ports and up to five instructions per. Cycle. The executives have also been reorganized slightly, with Sunny Cove having an additional device capable of handling LEA instructions (a very versatile x86 instruction that can perform different arithmetic operations as well as calculate memory addresses) and another for vector shuffles . This will give the machines out of order more options for planning instructions and thus increasing parallelism.

Where Skylake can perform two loads and one store per. Cycle, Sunny Cove detects this for two loads and two stores. The conversion buffer is larger, allowing for more out-of-order instructions in flight, and load and storage buffers are also larger, enabling more in-flight memory operations.

Like the oddball Cannon Lake processor, built about 10nm and shipment in limited quantities, Sunny Cove supports the AVX-512 instructions. The AVX-512 spans many different extensions and capabilities; Some are general purpose vector arithmetic, others are specialized in workloads such as neural networks. In addition to these, Sunny Cove will contain new instructions for acceleration of encryption and data compression workloads – these are the new instructions that are responsible for the 75 percent improvement.

Petabouts of RAM

Sunny Cove also makes the first major change to x64 virtual memory support when AMD introduced its x86-64 64-bit extension to x86 in 2003. Although the virtual memory addresses used on these systems take 64 bits to save, they contain only In fact, 48 useful bits of information. Bits 0 to 47, with the top 16 bits, 48 ​​to 63, all copies of bit 47 are used. This limits virtual address space to 256TB. These virtual addresses are mapped to physical addresses using a four-page page table structure, where physical memory addresses are also limited to 48 bits. This means that these systems can support a maximum of 256TB of physical memory.

Both Intel and AMD have participated in these limits since 2003. No longer: Sunny Cove expands virtual addresses to 57 meaningful bits (with the 7 best bits again, either all zeros or all, copy bit 56), with physical memory addresses of up to 52 bits. To handle this, a fifth level is required in the sidebar. The new limits enable 128PB virtual address space and 4PB physical memory.

The different iterations of Skylake have provided us with improved clock speeds and increasing core counts. What they have not done, however, is to improve the IPC for single-threaded code. For the first time since 2015, that's what Sunny Cove will do, which makes every workload faster, not just those that can spread to an ever larger number of threads.

Intel is promising Core branded Sunny Cove CPU in the second half of 2019. By 2020, this will be followed by Willow Cove, a Sunny Cove with a redesigned cache, new security features and new transistor optimization. By 2021, the company released Golden Cove, again with more security features, but also promising enhanced single-threaded performance, better machine-learning performance and better network and 5G performance.

Sunny Cove also comes to Xeon. The roadmap here is vaguer-Intel does not offer any dates – but will see Cascade Lake in the early part of 2019, which brings some new AVX-512 instructions to neural networks and as many as 48 cores. This will be followed by Cooper Lake, which will include support for bfloat16 data- a reduced precision floating point format used in neural networks. This will be followed by Sunny Cove in its Xeon cover: Ice Lake. A next-gen processor will follow from there.

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