More and more difficult process, more and more complex chip design, where is the future? As a leader in the industry, Intel has also proposed a new and more flexible approach when designing new CPUs, GPU architectures and products.
On the architecture day the eventIntel demonstrated a new 3D chip packaging technology called "Foveros", which introduced the 3D stack design for CPU processors for the first time. It can realize chip stacked chips and integrate chips of different processes, structures and applications. The second half of 2019 began to be launched.
Intel said that technology offers great flexibility that designers can "mix and match" different technology patch modules, different memory chips, I / O configuration in a new product form and enable the product to be broken down into smaller "Chip combination."
Intel has first undergone the difficulties with new process advances in recent years, especially for high performance computing chips. The 14nm process has been in use for four years, which was unthinkable earlier.
However, Intel's generation of processes is not only one, but different optimizations for different uses of the chip, such as the I / O chipset, have actually evolved.
For the next generation of process planning, Intel has three levels, first for the calculated 1274 10nm process, which will be optimized for 1274.7, 1274.12 (10nm +, 10nm ++), and for I / O is 1273 for the new Foveros. Then the P1222 is designed and no further optimization is required in the short term.
Then the computer enters the chipfrom
1276 7nmProcess generation, IO, Foveros will also develop at the same time as for the futurefrom
1278The chip computing process is still under review and no accident should correspond to 5nm.
According to Intel, the demand for transistor density is very different for different uses of chips or functional modules. Performance, power consumption and cost are also very different. Therefore, all chip modules use the same process that does not achieve the best results, especially the new process. It gets harder and harder, it's not worth it and it gets harder and harder.
Intel was previously launchedfrom
EMIB (Embedded Multi-Chip Interconnect Bridge) 2D Packaging TechnologyFor this purpose, the typical product is the Kaby Lake-G processor, which integrates the AMD Vega GPU graphics core.
Foveros is upgraded to a 3D package that switches the multi-chip package from a single plane to a stereo combination, greatly increasing the integration density and allowing for a more flexible combination of different chips or functional modules.
This is a schematic diagram of the 3D Foveros 3D package:from
Bottom is the packing substrate on which a Bottom Chip is located, which acts as an active interposer.– AMD Fiji / Vega core integrated package HBM memory has a similar existence.
A number of new products or modules can be placed on top of the intermediate layer., such as CPU, GPU, memory, baseband …
There are a large number of TSV 3D silicon perforations in the interposerResponsible for the solder supports over and above, enabling the top chip and module to communicate with other parts of the system.
Intel already has a sample of Foveros chips and said it is ready for mass production.Next year, the first product will be launched, which is the little guy above, Intel calls it"Hybrid x86 processor" (Hybrid x86 CPU).
This little chipfrom
Length and width are only 12 x 12 mm and the height is only 1 mm.There is not yet a coin, but the internal 3D stack encapsulates more modules.
Over the bottomfrom
IO chip of P1222 22FFL (22nm work type) processLow price and low leakage.
P1274 10nm process computing chip, also known as the traditional CPU, integrates a Sunny Core high performance core and four Atom low-power kernels (perhaps the new Tremont architecture).
Going up even longerfrom
PoP integrated packet memory chip.
Intel claims itIts standby power consumption is only 2mW, which is 0.002W, and the maximum power consumption is no more than 7W.Of course it is for the mobile platform, and it does not require a fan, but the specific unit of measurement did not say.
Let's look at the internal composition of this processor: the top right corner is a single Sunny Cove CPU kernel, with a dedicated 0.5MB MLC intermediate cache, the upper left corner is the LPDDR4X controller, the bit width is four channels at 4 × 16 bit and four A small CPU core that shares 1.5 MB L2 cache.
In the middle there is a 4MB final cache, while the bottom part is distributed with a low-power version of 11th generation (64 EU devices), 11.5 generation display controller, DisplayPort 1.4 controller and various other modules.
However, on-site demonstration prototype platform also uses a small fan, in addition to seeing PCI-E M.2 interface, UFS flash memory, multiple SIM connectors –from
Will Intel re-enter the mobile phone processor?
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