Next year, AMD will launch 7-nm EPYC server processors on the Zen 2 architecture, where a formal message was delivered half a month ago. A two-socket system based on a pair of 64-core flagship engineering samples was recently seen in the SiSoftware Sandra test suite database, thereby highlighting the technical characteristics of the upcoming CPU.
Revocation of second generation AMD EPYC processors is a multi-chip module that is assembled with eight 7-nm "chiplets", each containing eight Zen 2 cores and a 14-nm I / O chip containing an 8-channel DDR4 memory controller and a PCI Express 4.0 interface controller and other peripherals.
According to the post in the SiSoftware database, each of the "chiplets" immediately contains 32 MB cache on the third level, evenly distributed between two four-core CCX devices. In other words, the volume of L3 cache, when switching from Zen / Zen + architecture to Zen 2, will grow exactly twice. The total third-level cache in 64-core AMD EPYC is an impressive 256 MB.
Regarding the operating frequencies judged by the 2S1404E2VJUG5_20 / 14_N mark, the sample runs in SiSoftware at a nominal speed of 1.4 GHz, and in boost mode it can accelerate up to 2 GHz. Note that when releasing its frequency, it should grow to 2.35 GHz.